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Intel CEO Lip-Bu Tan On Stage At Intel Foundry Direct Connect With Synopsys President And CEO ...
More Sassine Ghazi In a joint announcement reflecting the growing importance of ecosystem collaboration in semiconductor design, Synopsys and Intel Foundry have expanded their partnership in support of chip development on Intel’s 18A and 18A-P process technologies. This engagement aims to streamline and scale next-generation chip design for applications in AI, HPC, data center, client PC and mobile platforms. As Intel continues to evolve its foundry strategy under the leadership of its new CEO Lip-Bu Tan , collaborations with EDA and core IP providers like Synopsys are key to enabling a competitive and accessible design infrastructure for customers targeting Intel’s new advanced process nodes.
At the center of the announcement is Intel’s 18A chip process, which introduces RibbonFET (Intel’s gate-all-around transistor design) and PowerVia (backside power delivery), among other cutting-edge semiconductor design technologies. These innovations are key enablers that improve both performance and power efficiency of chips built on Intel processes at scale. Intel’s 18A-P variant builds on this by offering additional optimization for performance-critical applications, and with better transistor density as well.
Synopsys Electronic Design Automation Tools And IP Solutions To Accelerate Chip Design On Intel 18A To help design teams adopt these nodes effectively, Synopsys has certified its digital and analog EDA flows for Intel 18A, and those flows are now production-ready for 18A-P. Synopsys also provides a broad library of silicon-proven IP, including chip and system interfaces and foundation IP essential for building advanced system-on-chip designs. The availability of validated tools and IP is critical for customers seeking to reduce development timelines and manage risk when targeting these advanced chip fab nodes.
In addition to process design support, the partnership also includes an optimized EDA reference flow for Intel’s EMIB-T (Embedded Multi-die Interconnect Bridge Technology), a 2.5D advanced chip packaging solution that facilitates high-bandwidth integration across multiple dies within a single package. The reference flow supports a unified exploration-to-signoff platform, allowing design teams to manage 2.
5D and 3D multi-die architectures more efficiently. This is particularly relevant as chip and system-level integration increasingly supplements traditional semiconductor node scaling (Moore’s Law) in driving performance and functionality. Intel EMIB-T 2.
5D Packaging Technology For Multi-Die System On Chip Designs EMIB-T and related advanced chip packaging technologies are an Intel strong suit for next-generation designs, particularly in data center AI applications, where compute density with better memory proximity helps drive performance. A certified EDA flow can reduce the complexity associated with these packaging technologies and support greater adoption across the industry. Looking ahead, Synopsys and Intel Foundry are also working together on early design enablement for Intel’s 14A-E node, which is currently in development.
While technical details are still scarce, 14A-E is expected to extend the architectural and manufacturing improvements introduced with 18A with 15 to 20% better performance-per-watt characteristics. By engaging early in the development of tools, flows and IP for 14A-E, the two companies aim to ensure that design infrastructure is in place when the process becomes commercially available, currently slated for late 2026 into early 2027. This approach reflects a broader trend toward concurrent design tool process co-optimization as process chip manufacturing nodes become more complex.
This collaboration is aligned with Intel Foundry’s broader strategy to build a complete ecosystem of tools, IP, and packaging capabilities that lower the barrier for entry for fabless semiconductor companies, like NVIDIA, Qualcomm, AMD, Broadcom, hot chip and tech start-ups, and many others. Having production-ready flows and validated IP in place is essential for serving both internal product groups at Intel and external customers. For Synopsys, the partnership reinforces its leadership in EDA enablement at advanced nodes and its commitment to supporting emerging packaging and system-level design methodologies.
As complexity rises across the design stack, the need for integrated, validated solutions will continue to grow. From a market perspective, the announcement reflects how ecosystem partnerships are becoming foundational to delivering innovation at the angstrom scale. By working in parallel across process development, packaging and design flows, Intel and Synopsys customers can mitigate risk and shorten development cycles.
The expanded collaboration between Synopsys and Intel Foundry provides a structured path for design teams targeting Intel’s advanced process technologies, including 18A, 18A-P, and the future 14A-E node. With certified EDA flows, a broad IP portfolio, and advanced packaging support for EMIB-T, the partnership addresses key challenges in modern chip development. It will be interesting to track how the two companies progress as new external customers adopt Intel’s 18A and advanced process nodes for state-side manufacturing here in the US.
Dave co-founded and is principal analyst at HotTech Vision And Analysis, a tech industry analyst firm specializing in consulting, test validation and go-to-market strategies for major chip and system OEMs. Like all analyst firms, HTVA provides paid services, research and consulting to many chip manufacturers and system OEMs, including companies mentioned in this article. However, this does not influence his objective coverage.
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