1 day Ago By Tobias Mann
Direct Connect Intel has revealed a pair of variants of its long-awaited 18A process node to make it better suited for, one, manufacturing mass-market processors and, two, complex multi-die semiconductors for – of course – AI. First teased in mid-2021, the 2nm-ish 18A is set to finally enter volume production later this year with the launch of Intel’s Panther Lake client processor family. However, the node was only really intended for specialist high-performance use cases — think high-end CPUs and GPUs — with its forthcoming 14A process node set to be the chipmaker’s first truly mass-market node.
Unfortunately, while 14A promises to deliver a 15-20 percent performance per watt uplift, it’s still a few years away from volume production. Faced with growing demand, particularly for American-made silicon, Intel has decided it needs something to satiate the masses a little sooner and has tweaked its original 18A formula with two new revisions: One designed to address a broad range of applications, and another tuned for, you guessed it, multi-die AI accelerators. The first of these is called 18A-P, and promises another 8 percent performance per watt improvement over the base 18A node.
More importantly, for customers already evaluating designs on 18A, Intel Chief Global Operations Officer Naga Chandrasekaran claimed transitioning to the newer node should be seamless. The other variant is called 18A-PT and is optimized for designs requiring through silicon vias (TSVs), which allow communication and power delivery through silicon and means chips can be assembled by stacking them on top of one another. At the x86 titan's Foundry Direct Connect 2025 event on Tuesday, SVP and GM of Intel Foundry Kevin O'Buckley teased a concept AI accelerator which will sandwich a load of speedy SRAM tiles between an AI accelerator or CPU die and a base die built on 18A-PT.
Here's a look at the kinds of chips Intel says customers are now asking it for - Click to enlarge "This is what our customers are telling us they need us to deliver for them. It's a 3D construction with multiple fully-utilized base reticle dies with many compute dials stacked on top. It's surrounded by an extraordinary massive memory capacity, both the highest performing HBM and also, in this case, LPDDR dies.
And these are all coherently connected by both electrical and optical interfaces with tens of terabits of bandwidth," he explained. "We believe, based on what our customers are telling us, that we are uniquely positioned across the entire industry to deliver these massive, heterogeneous systems on a package." If that sounds massively complex and risky, know that Intel is not alone in suggesting such designs.
AMD and TSMC have used both advanced packaging tech, and TSVs to boost compute density or SRAM capacity beyond what's practical using conventional manufacturing techniques. In fact Intel's concept strikes us as a mash up of AMD's MI300X and Genoa-X CPUs and GPUs. Perhaps more importantly, Intel already has considerable experience with both 2.
5D and 3D packaging with its EMIB and Foveros tech, which it used extensively in its last datacenter GPU, codenamed Ponte Vecchio . With advanced packaging required for most AI accelerators, Intel is now taking steps to extend these packaging techniques to customer designs requiring large quantities of compute and memory at a lower cost, Chandrasekaran explained. To this end, the company has announced a collaboration with silicon packaging and test provider Amkor to offer its manufacturing tech to a broader number of customers.
The tie up with Amkor is hardly surprising, given that TSMC is also working with the firm to offer its CoWoS packaging tech in the US market. The developments announced Tuesday reflect newly minted CEO Lip-Bu Tan's commitment to seeing his predecessor Pat Gelsinger’s vision of Intel becoming a chipmaker-for-hire foundry through to completion. But rather than the aspirational promises offered at Intel’s foundry event in 2024, this year's edition was far more pragmatic.
Rather than claims of overtaking Samsung Electronics’ foundry market share, Tan explained how Intel is clearing barriers to adoption of its foundry services, building trust in its process and packaging tech, and working to reclaim process leadership. "This is truly a service business, and that is built on the foundational principle of trust and you have to be patient to earn your trust," Tan said, adding that Intel must deliver performance, reliability, and yields that meet customer expectations. A key aspect of this plan, it's clear, involves capitalizing on demand for American-made semiconductors spurred by the Trump administration's efforts to catalyze US manufacturing.
"We are the only company that does advanced, leading-edge semiconductor R&D and manufacturing in the United States," Tan noted. However Intel is not alone in manufacturing leading-edge silicon in the USA as TSMC is already churning out 3nm parts on American soil. Tan also went to great pains to downplay the risks of doing business with Intel’s fledgling foundry unit.
CEOs of Synopsys, Cadence Systems (which Tan used to run), and Siemens EDA were brought on stage to highlight its close collaboration with industry's top electronic design automation vendors. "One of my top priorities is to make it easier for the ecosystem to do business with Intel," he said. However, as we saw last week, Intel's foundry unit continues to struggle financially, with the division posting a $2.
3 billion operating loss. The situation is expected to improve as Intel stops outsourcing production of its own chips to TSMC when Panther Lake debuts later this year. In the meantime, Tan is looking to "de-laborize" Intel's workforce, promising another round of layoffs, which according to some reports could see as much as 20 percent of Chipzilla's workforce culled.
®.
